# pacman -Syuu :: 正在同步软件包数据库... 错误：无法从 repo.msys2.org : Operation too slow. Less than 1 bytes/sec transferred the last 10 seconds 获取文件 'mingw32.db'] 49% 错误：无法从 sourceforge.net : Operation too slow. Less than 1 bytes/sec transferred the last 10 seconds 获取文件 'mingw32.db' 3% 错误：无法从 www2.futureware.at : Operation too slow. Less than 1 bytes/sec transferred the last 10 seconds 获取文件 'mingw32.db'7% 错误：无法从 mirror.yandex.ru : Operation too slow. Less than 1 bytes/sec transferred the last 10 seconds 获取文件 'mingw32.db' 10% 错误：无法升级 mingw32 (下载数据库出错)
Server = https://mirrors.tuna.tsinghua.edu.cn/msys2/mingw/i686
编辑 /etc/pacman.d/mirrorlist.mingw64 ，在文件开头添加：
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Server = https://mirrors.tuna.tsinghua.edu.cn/msys2/mingw/x86_64
编辑 /etc/pacman.d/mirrorlist.msys ，在文件开头添加：
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Server = https://mirrors.tuna.tsinghua.edu.cn/msys2/msys/$arch
然后执行 pacman -Sy 刷新软件包数据即可。
Step3: Install Verilator
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pacman -Syuu #Close the MSYS2 shell once you're asked to pacman -Syuu pacman -S --needed base-devel mingw-w64-x86_64-toolchain \ git flex\ mingw-w64-x86_64-cmake
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pacman -S mingw-w64-x86_64-verilator
Step4: Add to ENV
Add D:\msys64\usr\bin;D:\msys64\mingw64\bin to you windows PATH
Step4: Spinal simulation by verialtor
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[Progress] Verilator compilation started VDFT2Cell.mk:67: /mingw64/share/verilator/include/verilated.mk: No such file or directory make: *** No rule to make target '/mingw64/share/verilator/include/verilated.mk'. Stop. Exception in thread "main" java.lang.AssertionError: assertion failed: Verilator C++ model compilation failed at scala.Predef$.assert(Predef.scala:170) at spinal.sim.VerilatorBackend.compileVerilator(VerilatorBackend.scala:376) at spinal.sim.VerilatorBackend.<init>(VerilatorBackend.scala:429) at spinal.core.sim.SpinalVerilatorBackend$.apply(SimBootstraps.scala:120) at spinal.core.sim.SpinalSimConfig.compile(SimBootstraps.scala:400) at spinal.core.sim.SpinalSimConfig.compile(SimBootstraps.scala:364) at FFT.DFT2CellTest$.main(FFTsim.scala:27) at FFT.DFT2CellTest.main(FFTsim.scala)
x86_64-w64-mingw32-g++.exe: error: /d/msys64/mingw64/share/verilator/include/verilated.cpp: No such file or directory x86_64-w64-mingw32-g++.exe: fatal error: no input files compilation terminated. make: *** [/d/msys64/mingw64/share/verilator/include/verilated.mk:192: verilated.o] Error 1 make: *** Waiting for unfinished jobs.... x86_64-w64-mingw32-g++.exe: error: /d/msys64/mingw64/share/verilator/include/verilated_vcd_c.cpp: No such file or directory x86_64-w64-mingw32-g++.exe: fatal error: no input files compilation terminated. Exception in thread "main" java.lang.AssertionError: assertion failed: Verilator C++ model compilation failed
任然遇到问题： 检查环境变量Paht的值为C:\Users\Administrator\.babun\cygwin\bin;D:\Program\emacs-26.2\bin;C:\Users\Administrator\.babun;C:\Users\Administrator\AppData\Roaming\npm;%IntelliJ IDEA Community Edition%;C:\Users\Administrator\AppData\Local\Pandoc\;c:\msys64\usr\bin\;c:\msys64\mingw64\bin\ 发现很乱 ,删除一些不用的 D:\Program\emacs-26.2\bin;C:\Users\Administrator\.babun;C:\Users\Administrator\AppData\Local\Pandoc\;c:\msys64\usr\bin\;c:\msys64\mingw64\bin\; 更新PATH
how to keep chisel variable name when generate verilog
There are several reasons why a name may be disappearing.
Constant Propagation For many reasons, including interoperability with existing CAD tools, performance, and Verilog debug-ability, Chisel (actually the FIRRTL compiler underneath Chisel) will propagate constants and direct wire connections. For example:
# The following portion is depending on the EDA tools you are using, Please add them by yourself according to your EDA vendors SIM_TOOL := vcs # this is a free solution here to use iverilog to compile the code SIM_OPTIONS := -sverilog -debug_all +incdir+${INC_DIR} -timescale=1ns/100ps +notimingcheck +nospecify +v2k +memcbk -fsdb -l com.log SIM_EXEC := ${RUN_DIR}/simv -l sim.log +notimingcheck +nospecify +loopreport +memcbk +novopt
WAV_TOOL := verdi #To-ADD: to add the waveform tool WAV_OPTIONS := -timescale=1ns/100ps +notimingcheck +nospecify #To-ADD: to add the waveform tool options WAV_PFIX := #To-ADD: to add the waveform file postfix
