Chisel组合逻辑时序逻辑

实例1
  val tiRomStartAddr = RegInit(0.U(6.W))  //显示的声明Reg
  when      (io.swif.K<40.U  ){tiRomStartAddr :=  25.U }
  .elsewhen (io.swif.K<159.U ){tiRomStartAddr :=  21.U }
  .elsewhen (io.swif.K<200.U ){tiRomStartAddr :=  35.U }
  .elsewhen (io.swif.K<481.U ){tiRomStartAddr :=  15.U }
  .elsewhen (io.swif.K<530.U ){tiRomStartAddr :=  10.U }
  .elsewhen (io.swif.K<2881.U){tiRomStartAddr :=   5.U }
  .otherwise                  {tiRomStartAddr :=  25.U }
实例2
  val RRomRdata = RegInit(0.U(log2Up(pm.MaxR).W)) //显示的声明Reg并初始化（switch语句不带default)
  switch (io.RRomAddr) {
    is (0.U) {RRomRdata := intraRowTi.RRomVal(0).U}
    is (1.U) {RRomRdata := intraRowTi.RRomVal(1).U}
    is (2.U) {RRomRdata := intraRowTi.RRomVal(2).U}
    is (3.U) {RRomRdata := intraRowTi.RRomVal(3).U}
    is (4.U) {RRomRdata := intraRowTi.RRomVal(4).U}
    is (5.U) {RRomRdata := intraRowTi.RRomVal(5).U}
    is (6.U) {RRomRdata := intraRowTi.RRomVal(6).U}
    is (7.U) {RRomRdata := intraRowTi.RRomVal(7).U}
  }

实例1
  val tiRomStartAddr = Wire(UInt()) //显示的声明Wire
  when      (io.swif.K<40.U  ){tiRomStartAddr :=  25.U }
  .elsewhen (io.swif.K<159.U ){tiRomStartAddr :=  21.U }
  .elsewhen (io.swif.K<200.U ){tiRomStartAddr :=  35.U }
  .elsewhen (io.swif.K<481.U ){tiRomStartAddr :=  15.U }
  .elsewhen (io.swif.K<530.U ){tiRomStartAddr :=  10.U }
  .elsewhen (io.swif.K<2881.U){tiRomStartAddr :=   5.U }
  .otherwise                  {tiRomStartAddr :=  25.U }

实例2
  val RRomRdata = Wire(UInt())   //显示的声明Wire     
  RRomRdata := 0.U               //一定要设默认值，否则组合逻辑条件不全chisel编译不过（verilog组合逻辑条件不全会产生锁存器）
  switch (io.RRomAddr) {
    is (0.U) {RRomRdata := intraRowTi.RRomVal(0).U}
    is (1.U) {RRomRdata := intraRowTi.RRomVal(1).U}
    is (2.U) {RRomRdata := intraRowTi.RRomVal(2).U}
    is (3.U) {RRomRdata := intraRowTi.RRomVal(3).U}
    is (4.U) {RRomRdata := intraRowTi.RRomVal(4).U}
    is (5.U) {RRomRdata := intraRowTi.RRomVal(5).U}
    is (6.U) {RRomRdata := intraRowTi.RRomVal(6).U}
    is (7.U) {RRomRdata := intraRowTi.RRomVal(7).U}
  }      

实例3
  val PrimeRom = Vec(PrimeAndRoot.map(_.U)) //ROM默认生成的是组合逻辑，寄存器输出自己加一级
  io.out3 := PrimeRom(io.i)