• Q1:

• Q1:

如何查看当前使用的chisel版本

一般情况下chisel的版本会在build.sbt里显式定义，但有时候像jupter-notebook里并不能看到版本号
这种情况下有一个方法可以得到版本号
即生成的firrtl文件头会打印版本信息

• [ ] BitPat length bugs
  BitPat.pare("b1100_0000") = (192,255,9) 实际8bit，返回9bit
  BitPat.pare("b11000000") = (192,255,8)

  1 2 3

  35: (bits, mask, x.length - 1) fix 剔除字符'_' 后统计长度 35: (bits, mask, x.filter(_!='_').length - 1)

• [ ] bug2

how to keep chisel variable name when generate verilog

There are several reasons why a name may be disappearing.

Constant Propagation
For many reasons, including interoperability with existing CAD tools, performance, and Verilog debug-ability, Chisel (actually the FIRRTL compiler underneath Chisel) will propagate constants and direct wire connections. For example:

Chisel 不同开发生产的Verilog 模块名冲突

同学A 负责开发AP
同学B 负责开发CP
其中都会用到Queue，生产的AP_system_top.v CP_system_top.v中可能都会包含一个
module Queue (
集成到SOC_top.v时会面临模块名冲突的问题，目前Chisel 本身没有提供解决该问题的方法。
只能依赖于原始verilog 的解决方法

时序逻辑的声明和写法

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实例1
  val tiRomStartAddr = RegInit(0.U(6.W))  //显示的声明Reg
  when      (io.swif.K<40.U  ){tiRomStartAddr :=  25.U }
  .elsewhen (io.swif.K<159.U ){tiRomStartAddr :=  21.U }
  .elsewhen (io.swif.K<200.U ){tiRomStartAddr :=  35.U }
  .elsewhen (io.swif.K<481.U ){tiRomStartAddr :=  15.U }
  .elsewhen (io.swif.K<530.U ){tiRomStartAddr :=  10.U }
  .elsewhen (io.swif.K<2881.U){tiRomStartAddr :=   5.U }
  .otherwise                  {tiRomStartAddr :=  25.U }
实例2
  val RRomRdata = RegInit(0.U(log2Up(pm.MaxR).W)) //显示的声明Reg并初始化（switch语句不带default)
  switch (io.RRomAddr) {
    is (0.U) {RRomRdata := intraRowTi.RRomVal(0).U}
    is (1.U) {RRomRdata := intraRowTi.RRomVal(1).U}
    is (2.U) {RRomRdata := intraRowTi.RRomVal(2).U}
    is (3.U) {RRomRdata := intraRowTi.RRomVal(3).U}
    is (4.U) {RRomRdata := intraRowTi.RRomVal(4).U}
    is (5.U) {RRomRdata := intraRowTi.RRomVal(5).U}
    is (6.U) {RRomRdata := intraRowTi.RRomVal(6).U}
    is (7.U) {RRomRdata := intraRowTi.RRomVal(7).U}
  }

chisel-example \ chisel-tutorial 同样代码，生成器输出不一致问题

同样的一份代码
src/main/scala/GCD.scala
src/test/scala/GCDTester.scala

其中生成vcd波形的代码

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object GCDTester extends App {
  iotesters.Driver.execute(Array("--target-dir", "generated", "--fint-write-vcd"), () => new GCD){
    c => new GCDTests(c)
  }
}

Chisel 查找表电路优先级问题

verilog ROM的两种写法及区别

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方法1
always @(posedge clk )
begin
    case(addr0)  
        6'd0 :  data0 <= 8'd214;
        6'd1 :  data0 <= 8'd213;
        6'd2 :  data0 <= 8'd212;
        6'd3 :  data0 <= 8'd211;
        6'd4 :  data0 <= 8'd210;
        6'd5 :  data0 <= 8'd209;
        6'd6 :  data0 <= 8'd208;
        6'd7 :  data0 <= 8'd207;   
方法2
always @(posedge clk )
begin
         if(addr1 == 6'd0 )  data1 <= 8'd150;
    else if(addr1 == 6'd1 )  data1 <= 8'd149;
    else if(addr1 == 6'd2 )  data1 <= 8'd148;
    else if(addr1 == 6'd3 )  data1 <= 8'd147;
    else if(addr1 == 6'd4 )  data1 <= 8'd146;
    else if(addr1 == 6'd5 )  data1 <= 8'd145;
    else if(addr1 == 6'd6 )  data1 <= 8'd144;
    else if(addr1 == 6'd7 )  data1 <= 8'd143;

方法2是不是带优先级？ 实际上是不带优先级
逻辑上if取的条件都是addr1的值，一定是互斥的，综合工具也能自动识别出这种if else
它有别于以下这种情况，这种情况下是真实带有优先级的电路，其中another_cond_A,another_cond_B
是独立的两个输入条件，和addr1的取值可能同时发生，所以不能被综合器当做查找表来对待。