时序分析
静态时序分析工具STA，在分析时序的时候会统一从一个点出发开始计算分析（这样才有可行性），往往是从时钟PLL出来以后开始计算
一般情况下都会设一个clock network delay 表示从PLL 到寄存器段clk的群延迟 ，理想情况下，到每个寄存器的群延迟都是一样的（时钟balance）
看一个timing报告：
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| ****************************************
Startpoint: U_xx/_ram_sp1024x8/srsp_1024x8
(rising edge-triggered flip-flop clocked by clk)
Endpoint: U_xx/nS_bit_reg_1_
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
xx_top ZeroWireload tef40ulp128x8hd_ph_ssg0p99v2p25vm40c
Point Incr Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.0000 0.0000
clock network delay (ideal) 2.0000 2.0000
xx/srsp_1024x8/CLK (sadr41p1024x8m4b1) 0.0000 2.0000 r
xx/srsp_1024x8/Q[0] (sadr41p1024x8m4b) 2.2361 4.2361 f
xx/U37/X (SVN_ND2_T_2) 0.0290 4.2651 r
xx/U47/X (SVN_ND2_2) 0.0323 4.2974 f
....
..
xx/U188/X (SVN_EN2_F_1) 0.0956 4.8690 f
xx/nS_bit_reg_1_/D (SVN_FSDPRBQ_D_4) 0.0000 4.8690 f
data arrival time 4.8690
clock clk (rise edge) 3.3300 3.3300
clock network delay (ideal) 2.0000 5.3300
clock uncertainty 0.3000 5.0300
xxx/nS_bit_reg_1_/CK (SVN_FSDPRBQ_D_4) 0.0000 5.0300 r
library setup time 0.3303 4.6997
data required time 4.6997
--------------------------------------------------------------------------
data required time 4.6997
data arrival time -4.8690
--------------------------------------------------------------------------
slack (VIOLATED) -0.1693
****************************************
|
Clock Setup Slack = Data Required Time – Data Arrival Time
Clock Arrival Time = Latch Edge + Clock Network Delay to Destination Register
Data Required = Clock Arrival Time – μtSU – Setup Uncertainty
Data Arrival Time = Launch Edge + Clock Network Delay Source Register + μtCO + Register-to-Register Delay
