VCS仿真option

RUN_DIR      := ${PWD}

TESTCASE     := 00
DUMPWAVE     := 1

VSRC_DIR     := ${RUN_DIR}/../rtl
VTB_DIR      := ${RUN_DIR}/../tb
INC_DIR      := ${RUN_DIR}/../rtl/dir_inc_defines1
INC_DIR      += ${RUN_DIR}/../rtl/dir_inc_defines2
# TESTNAME     := $(notdir $(patsubst %.dump,%,${TESTCASE}.dump))
TESTNAME     := case${TESTNAME}
TEST_RUNDIR  := ${TESTNAME}

RTL_V_FILES  := $(wildcard ${VSRC_DIR}/*/*.v)
TB_V_FILES   := $(wildcard ${VTB_DIR}/*.v)

# The following portion is depending on the EDA tools you are using, Please add them by yourself according to your EDA vendors
SIM_TOOL     := vcs # this is a free solution here to use iverilog to compile the code
SIM_OPTIONS  := -sverilog -debug_all +incdir+${INC_DIR} -timescale=1ns/100ps +notimingcheck +nospecify +v2k +memcbk -fsdb -l com.log 
SIM_EXEC     := ${RUN_DIR}/simv -l sim.log +notimingcheck +nospecify +loopreport +memcbk +novopt

WAV_TOOL     := verdi #To-ADD: to add the waveform tool
WAV_OPTIONS  := -timescale=1ns/100ps +notimingcheck +nospecify #To-ADD: to add the waveform tool options 
WAV_PFIX     := #To-ADD: to add the waveform file postfix

all: run

compile.flg: ${RTL_V_FILES} ${TB_V_FILES}
    @-rm -rf compile.flg
    ${SIM_TOOL} ${SIM_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} ;
    touch compile.flg

compile: compile.flg 

wave: 
    # gvim -p ${TESTCASE}.spike.log ${TESTCASE}.dump &
    ${WAV_TOOL} ${WAV_OPTIONS} ${RTL_V_FILES} ${TB_V_FILES} & 

run: compile
    rm -rf ${TEST_RUNDIR}
    mkdir ${TEST_RUNDIR}
    cd ${TEST_RUNDIR}; ${SIM_EXEC} +DUMPWAVE=${DUMPWAVE} +TESTCASE=${TESTCASE} |& tee ${TESTNAME}.log; cd ${RUN_DIR}; 

.PHONY: run clean all